According to AMD, rather than invest in traditionally large and expensive enterprise-class proprietary hardware, the new Quad-Core AMD Opteron SE processors empower businesses to scale up a datacenter by moving to servers that can offer enterprise-class functionality at industry-standard pricing. Adding more cores to 4-socket and 8-socket x86 servers can allow users to gain greater levels of performance and efficiency which is necessary to handle database and virtualization applications. The new Quad-Core AMD Opteron SE processors will be available in systems from OEMs and solution providers including Hewlett-Packard, Sun Microsystems, Dell and IBM
Quad-Core AMD Opteron processor Models 2360 SE (2.5 GHz), 2358 SE (2.4 GHz), 8360 SE (2.5 GHz), and 8358 SE (2.4 GHz) are widely available and have already set performance benchmarks in business-relevant testing, AMD noted.
Tuesday, August 5, 2008
Intel ready with Atom processors for low-cost notebooks
Intel is ready to ship the latest edition of its Atom processor family, this time going after the emerging market for low-cost subnotebooks.
The N270 and N230 are processors designed for what Intel calls "netbooks" and "nettops," and the company plans to unveil them Tuesday at Computex in Taiwan. The new chips are basically the same chips as the earlier Atom processors released for mobile Internet devices, but they have been tweaked slightly for use with bigger Internet access devices, said Erik Reid, director of Intel's Mobile Platforms Group, on a conference call.
While the MID category is still very much a niche, the subnotebook is getting a fresh look in both emerging markets and more developed areas. Consumers have shown more than a passing interest in devices like the Eee PC as low-cost Internet access terminals. You're not going to want to edit the family reunion video on one of these things, but you can check sports scores and update your Facebook profile without too much difficulty.
Intel estimates that a netbook using the Atom N270 processor running at 1.6GHz, a 7-inch to 10-inch screen, 512MBs of RAM, and 2GBs to 4GBs of flash storage should cost around $250. The N270 processor for netbooks costs $44 in quantities of 1,000 units, while the N230 processor for nettops (think small desktops) costs $29.
The N270 and N230 are processors designed for what Intel calls "netbooks" and "nettops," and the company plans to unveil them Tuesday at Computex in Taiwan. The new chips are basically the same chips as the earlier Atom processors released for mobile Internet devices, but they have been tweaked slightly for use with bigger Internet access devices, said Erik Reid, director of Intel's Mobile Platforms Group, on a conference call.
While the MID category is still very much a niche, the subnotebook is getting a fresh look in both emerging markets and more developed areas. Consumers have shown more than a passing interest in devices like the Eee PC as low-cost Internet access terminals. You're not going to want to edit the family reunion video on one of these things, but you can check sports scores and update your Facebook profile without too much difficulty.
Intel estimates that a netbook using the Atom N270 processor running at 1.6GHz, a 7-inch to 10-inch screen, 512MBs of RAM, and 2GBs to 4GBs of flash storage should cost around $250. The N270 processor for netbooks costs $44 in quantities of 1,000 units, while the N230 processor for nettops (think small desktops) costs $29.
Xeon
The Xeon brand refers to many families of Intel's x86 multiprocessing CPUs – for dual-processor (DP) and multi-processor (MP) configuration on a single motherboard targeted at non-consumer markets of server and workstation computers, and also at blade servers and embedded systems. The Xeon brand has been maintained over several generations of x86 and x86-64 processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. Intel's (non-x86) IA-64 processors are called Itanium, not Xeon.
Revived architecture in Pentium M (Banias and Dothan)
Upon release of the Pentium 4's mobile variant, it was quickly realized that the new NetBurst core was not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Pentium 4-Mobile ran much hotter than the Pentium III-M and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Intel, realizing that their new architecture wasn't the best choice for the mobile space, went back to the drawing boards for a design that would be optimally suited for this market segment. The result was a hybrid, modernized P6 design called the Pentium M:
Design Overview[1]
* Socket 479. Electrically similar to Socket 478, but not compatible.
* Faster front side bus. With the initial Banias core, Intel adopted the 400 MT/s Netburst bus. The Dothan core moved to the 533 MT/s bus, following Pentium 4's evolution.
* Larger L2 cache. Initially 1 MiB, then 2 MiB in Dothan. Dynamic cache activation by quadrant selector from sleep states.
* SSE2 support.
* Pipelining lengthening by 3-4 stages for improved clock scaling.
* Dedicated register stack management.
* Addition of global history to branch prediction table.
* Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations.
* Enhanced SpeedStep III (EIST). The processor can clock down to a fraction of its maximum speed and voltage when idle, bringing power usage down to only a few Watts.
The Pentium M was the most power efficient processor for notebooks for several years, consuming under 30 Watts at maximum load and a mere 4-5 Watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Netburst processors clocked nearly one gigahertz higher and equipped with much more memory and bus bandwidth.[1]
Pentium M's primary shortcoming was in the floating point realm. The P6 core had formidable floating point performance throughout much of its lifetime, but the newer AMD Athlon and Athlon 64 cores, along with the powerful floating point SIMD capabilities of NetBurst processors, outclassed it. Although Intel implemented SSE2 in Pentium M, the implementation was not equal to that within the Athlon 64 or Pentium 4. So, on tasks where Pentium M was relying heavily on its floating point unit instead of its cache and integer performance, it would present disappointing performance.
Intel, realizing that their new architecture wasn't the best choice for the mobile space, went back to the drawing boards for a design that would be optimally suited for this market segment. The result was a hybrid, modernized P6 design called the Pentium M:
Design Overview[1]
* Socket 479. Electrically similar to Socket 478, but not compatible.
* Faster front side bus. With the initial Banias core, Intel adopted the 400 MT/s Netburst bus. The Dothan core moved to the 533 MT/s bus, following Pentium 4's evolution.
* Larger L2 cache. Initially 1 MiB, then 2 MiB in Dothan. Dynamic cache activation by quadrant selector from sleep states.
* SSE2 support.
* Pipelining lengthening by 3-4 stages for improved clock scaling.
* Dedicated register stack management.
* Addition of global history to branch prediction table.
* Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations.
* Enhanced SpeedStep III (EIST). The processor can clock down to a fraction of its maximum speed and voltage when idle, bringing power usage down to only a few Watts.
The Pentium M was the most power efficient processor for notebooks for several years, consuming under 30 Watts at maximum load and a mere 4-5 Watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Netburst processors clocked nearly one gigahertz higher and equipped with much more memory and bus bandwidth.[1]
Pentium M's primary shortcoming was in the floating point realm. The P6 core had formidable floating point performance throughout much of its lifetime, but the newer AMD Athlon and Athlon 64 cores, along with the powerful floating point SIMD capabilities of NetBurst processors, outclassed it. Although Intel implemented SSE2 in Pentium M, the implementation was not equal to that within the Athlon 64 or Pentium 4. So, on tasks where Pentium M was relying heavily on its floating point unit instead of its cache and integer performance, it would present disappointing performance.
AMD's Puma ready to pounce
Notebook makers of all stripes are getting ready to launch systems based on AMD's Puma notebook technology, which consists of a new processor, a mobile chipset, and wireless chips from AMD's partners. The official announcement is expected to come later Wednesday at the Computex trade show in Taiwan, and notebooks with the chips will be arriving over the next several weeks from companies like Acer, Dell, Hewlett-Packard, and Toshiba, said Bahr Mahony, director of AMD's mobile business.
Assuming those notebooks ship without incident, Puma arrives in far better shape than Barcelona, the quad-core server processor that was a year late after running into major technical glitches. Puma also arrives at a time when Intel has suffered a rare--at least over the last two years--gaffe inside its notebook group: the company's Montevina notebook platform will be delayed several weeks with chipset problems, which could affect Intel's performance during the important back-to-school shopping season.
AMD's new Turion X2 Ultra processor is the first designed-for-mobile processor that AMD has ever produced; the earlier versions of its Turion processor were essentially the same design as its Opteron design with a more power-friendly implementation.
Assuming those notebooks ship without incident, Puma arrives in far better shape than Barcelona, the quad-core server processor that was a year late after running into major technical glitches. Puma also arrives at a time when Intel has suffered a rare--at least over the last two years--gaffe inside its notebook group: the company's Montevina notebook platform will be delayed several weeks with chipset problems, which could affect Intel's performance during the important back-to-school shopping season.
AMD's new Turion X2 Ultra processor is the first designed-for-mobile processor that AMD has ever produced; the earlier versions of its Turion processor were essentially the same design as its Opteron design with a more power-friendly implementation.
Intel Core (Yonah)
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core versions were sold under the Core Solo and Core Duo brands respectively (the Solo processor being a Duo, but with one disabled core). These processors provided partial solutions to some of the foregoing Pentium M's shortcomings, by adding to its P6 microarchitecture:
* SSE3 Support
* Dual-core technology with shared L2 cache (restructuring processor organization)
This resulted in the interim microarchitecture for mobile only CPUs, part way between P6 and the next all processor Core microarchitecture introduced with the CPUs branded Core 2, Pentium Dual-Core, Celeron, and Xeon.
It is important to note, that some Pentium Dual-Core branded CPUs (T2060, T2080 and T2130) are Yonah-based.
* SSE3 Support
* Dual-core technology with shared L2 cache (restructuring processor organization)
This resulted in the interim microarchitecture for mobile only CPUs, part way between P6 and the next all processor Core microarchitecture introduced with the CPUs branded Core 2, Pentium Dual-Core, Celeron, and Xeon.
It is important to note, that some Pentium Dual-Core branded CPUs (T2060, T2080 and T2130) are Yonah-based.
From Pentium Pro to Pentium III
The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
* Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
* Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
* Integrated L2 cache that runs at the full speed of the processing core, instead of the earlier designs of off-die (on motherboard) cache, which runs at a fraction of the CPU frequency.
* Wider 36-bit physical address bus to support more than 4 GiB of physical memory (the linear address space of a process was still limited to 4 GiB).
* Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
Some techniques first used in the x86 space in the P6 core include:
* Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
* Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
* Integrated L2 cache that runs at the full speed of the processing core, instead of the earlier designs of off-die (on motherboard) cache, which runs at a fraction of the CPU frequency.
* Wider 36-bit physical address bus to support more than 4 GiB of physical memory (the linear address space of a process was still limited to 4 GiB).
* Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
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