From Pentium Pro to Pentium III

The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).

Some techniques first used in the x86 space in the P6 core include:

* Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
* Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
* Integrated L2 cache that runs at the full speed of the processing core, instead of the earlier designs of off-die (on motherboard) cache, which runs at a fraction of the CPU frequency.
* Wider 36-bit physical address bus to support more than 4 GiB of physical memory (the linear address space of a process was still limited to 4 GiB).
* Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.

The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.